1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device which can write, erase and read data at a high speed and at a low voltage.
2. Description of the Related Art
With enlargement of an application field such as a portable telephone and digital still camera, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has rapidly come into wide use. The EEPROM which permits electrical simultaneous erase of data is called a flash EEPROM.
The EEPROM is a non-volatile semiconductor memory device which stores digital information with two or more values according to whether or not a prescribed quantity of charges is stored and reads the digital information by a change in the conduction of a channel region corresponding to the quantity of charges.
The EEPROM is classified into a stacked-gate type and a split gate type. The split-gate type EEPROM is disclosed in e.g. U.S. Pat. Nos. 5,029,230, 5,045,488 and 5,067,108.
An arrangement of the split-gate type EEPROM cell is shown in FIGS. 5A and 5B. FIG. 5A is a plan view and FIG. 5B is a sectional view taken in line Xxe2x80x94X in FIG. 5A.
As seen from these figures, a drain region 102 and a source region 103 are formed on a P-type semiconductor substrate 101 by a prescribed interval spaced apart from each other. A channel region 104 is formed therebetween. A floating gate 106 is formed on a gate insulating film 105 over a region extending from a part of the channel region 104 to a part of the source region 103. A thick oxide film 107 (hereinafter referred to as xe2x80x9cminilocosxe2x80x9d) formed by selective oxidation is provided on the floating gate 106.
A tunnel oxide film 108 is formed to cover the side of the floating gate 106 and a part of the minilocos 107. A control gate 109 is formed from on the tunnel oxide film and a part of the channel region 104 to on a part of the drain region 102. On both sides of the EEPROM cell, element isolation oxide films 110 are formed so that it is electrically isolated from adjacent cells.
Now referring to FIGS. 6A-6C, an explanation will be given of the operation of the split-gate type EEPROM.
First, in write of data, as seen from FIG. 6A, prescribed voltages (e.g. 2 V for the control gate 109 and 10 V for the source region) are applied to the control gate 109 and source region 103) so that a current flows through the channel region 104. Thus, channel hot electrons (CHE""s) are injected into and stored in the floating gate 106. The capacitance coupling ratio between the control gate 109 and the floating gate 106 is as low as about 0.2 so that the voltage applied to the source region 103 boosts the potential of the floating gate 106 to promote the injection of CHE""s.
On the other hand, in erasure of data, as seen from FIG. 6B, with the drain region 102 and source region 103 connected to ground, a prescribed voltage (e.g. 13 V) is applied to the control gate 109 so that the electrons stored in the floating gate 106 are extracted as a Fowler-Nordheim tunneling current (FN tunnelling current) through the tunneling oxide film 108 to the control gate 109.
Further, in read of data, as shown in FIG. 6C, a prescribed voltage (e.g. 2 V) is applied to the control gate 109 and drain region 102. Then, a channel current corresponding to the quantity of charges stored in the floating gate 106 flows. By sensing the current, the data can be read.
The conventional split-gate type EEPROM described above has the following defects.
In the split-gate type EEPROM, a high electric field is produced in a gap between the control gate 109 and floating gate 106 so that the CHE""s are accelerated. This provides an advantage of a short programming time (time required to write data). However, this provides a disadvantage requiring a high voltage for the write and erasure of data.
On the other hand, in a stacked gate type EEPROM in which a control gate is formed on and in alignment with the floating gate, generally, write of data is made by CHE tunneling or FN tunneling, and erasure of data is made by the FN tunneling from the floating gate to the source region. However, this provides a disadvantage of a long programming time.
An object of the present invention is to provide a non-volatile semiconductor memory device which can write and erase data at a high speed using a low voltage.
Each aspect of the invention described below is separately illustrative of the various embodiments of the invention and is not intended to be restrictive of the broad invention.
In order to attain the above object, in accordance with the first aspect of the invention, there is a non-volatile semiconductor memory device comprising:
a drain region and a source region each formed of a semiconductor layer having a second conduction type which are formed apart from each other on a semiconductor substrate having a first conduction type;
a floating gate formed on a first insulating film over the semiconductor substrate between the drain region and the source region;
a channel region formed in a surface of the semiconductor substrate between one end of the floating gate and the drain region;
a control gate formed on an upper face and side face of the floating gate and the channel over a second insulating film; and
a semiconductor layer having the second conduction type enlarged from the source region to beneath the floating gate.
In accordance with this configuration, since the semiconductor layer having the second conduction type enlarged to beneath the floating gate is formed, a facing area between the source region and floating gate is increased. Therefore, the FN tunneling current flowing through the first insulating film is increased. As a result, write and erasure of data can be made within a short time.
In accordance with the second aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that the semiconductor layer having the second conduction type is a region enlarged from the source region to the drain side direction of the floating gate in the surface of the channel region.
In this configuration, the semiconductor layer having the second conduction type is enlarged from the source region to the drain side of the floating gate. Therefore, a facing area between the semiconductor layer and the floating gate can be maximized so that write and erasure of data can be made within a short time.
In accordance with the third aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that the semiconductor layer having the second conduction type is a region formed from the source region to reach the vicinity of the end of the floating gate on its drain side. In this configuration, since drain diffusion is made to reach the end position of the channel region beneath the floating gate semiconductor layer having the second conduction type, the facing area between the semiconductor layer and the floating gate can be maximized so that write and erasure of data can be made within a short time.
In accordance with the fourth aspect of the invention, the non-volatile semiconductor memory device according to the first invention is characterized in that the semiconductor layer having the second conduction type is a highly doped impurity region formed so as to generate tunneling between the semiconductor layer and the floating gate during write of data.
In accordance with the fifth aspect of the invention, the non-volatile semiconductor memory device according to any one of the first to the fourth aspect is characterized in that it further comprises a semiconductor layer having the first conduction type formed in the channel region.
In this configuration, although a short channel effect may occur because the channel length is shortened due to the provision of the semiconductor layer having the second conduction type, provision of the semiconductor layer having the first conduction type is arranged in the channel region so that occurrence of the short channel effect can be prevented.
In accordance with the sixth aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that the semiconductor layer is a region formed from the source region to reach the vicinity of the end of the floating gate on its drain side in a full width direction of the channel region.
In this configuration, since the source region is enlarged in a full width direction of the channel region, the facing area between the source region and the floating gate can be increased so that write and erasure of data can be made within a short time. Even where the source region is enlarged partially beneath the floating gate, the time required for write and erasure of data can be shortened.
In accordance with the seventh aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized that the semiconductor layer is a region formed from the source region to reach the vicinity of the end of the floating gate on its drain side partially in a width direction of the channel region, and
the source region is formed so that the remaining region of the channel region faces only a part of the floating gate.
In this configuration, a partial area of the channel region is used to increase the area facing the floating gate to shorten the time of write and erasure of data and the remaining area is used as a region for making read of data easy. As a result, the increase in a read voltage is prevented whereas the time required for write and erasure of data can be shortened.
In accordance with the eighth aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that it further comprises a semiconductor layer having the first conduction type formed between the semiconductor layer having the second conduction type and the drain region.
In this configuration, because the channel length is shortened due to the provision of the semiconductor layer having the second conduction type, provision of the semiconductor layer having the first conduction type is arranged in the channel region so that occurrence of the short channel effect can be prevented.
In accordance with the ninth aspect of the invention, there is provided a non-volatile semiconductor memory device comprising a drain region and a source region each having a second conduction type which are formed apart from each other on a semiconductor substrate having a first conduction type; a channel region formed between the drain region and the source region; a floating gate formed through a first insulating film on the semiconductor substrate between the drain region and the source region; and a control gate formed on the floating gate through a second insulating film, wherein
the non-volatile semiconductor memory device is divided into a first region and a second region in a width direction of the channel region; and
the first region includes a semiconductor layer having the second conduction type enlarged from the source region to beneath the floating gate, and another semiconductor layer having the first conduction type formed in the channel region.
In accordance with this configuration, in the first region, since the semiconductor layer having the second conduction type enlarged to beneath the floating gate is formed, a facing area between the source region and floating gate is increased. Therefore, the FN tunneling current flowing through the first insulating film is increased. By using this first region, write and erasure of data can be made within a short time. Further, in the first region, since the second conduction layer having the first conduction type is formed, the threshold voltage in this region is increased. This makes it difficult to read data using a low voltage. In order to obviate such an inconvenience, the second region (split-gate type EEPROM according to the prior art) is used to permit the data to be read.
In accordance with the tenth aspect of the invention, the non-volatile semiconductor memory device according to the fifth aspect is characterized in that a capacitance coupling ratio between the control gate and the floating gate is preferably 0.8 or larger. This decreases a potential difference between the control gate and floating gate during the write/erasure of data and increases the potential difference between the floating gate and the semiconductor layer having the second conduction type beneath it. Thus, since the FN tunneling current, the write/erasure of data can be effectively done using a low voltage, and deterioration of the read current is also prevented.
In accordance with the eleventh aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that film thicknesses of the first insulating film and the second insulating film are controlled so that a capacitance between the control gate and floating gate is equal to or larger than between the floating gate and the semiconductor layer having the second conduction type.
In this configuration, by adjusting the film thickness of each of the first and the second gate insulating film is adjusted to adjust the capacitance ratio so that write and erasure of data can be made at a low voltage.
In accordance with the twelfth aspect of the invention, the non-volatile semiconductor memory device according to the second aspect is characterized in that the control gate covers an entire surface of the floating gate through the insulating film.
Therefore, the capacitance coupling ration between the control gate and the floating gate is enhanced. This decreases a potential difference between the control gate and floating gate during the write/erasure of data and increases the potential difference between the floating gate and the first conductive layer having the second conduction type beneath it. Thus, the same effect as above can be obtained.
In accordance with the thirteenth aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that the semiconductor layer having the first conduction type is more deeply formed than a bottom of the semiconductor layer having the second conduction type is.
In this configuration, the short channel effect can be surely suppressed.
The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.